1. Field of Invention
This invention relates generally to semiconductor memories and specifically to circuits for providing a boosted voltage.
2. Description of Related Art
Many circuits such as, for instance, charge pumps, various MOS memory arrays, and so on, require a boosted input voltage for proper operation. A circuit which provides a boosted voltage of the type disclosed in U.S. Pat. No. 4,574,203, issued Mar. 4, 1986 to Baba, is shown in FIG. 1. Circuit 10 is coupled to receive an input clock signal IN and includes a PMOS pull-up transistor 12 coupled between a supply voltage V.sub.DD and an output terminal OUT and an NMOS pull-down transistor 14 coupled between the output terminal OUT and ground potential. The circuit 10 further includes a bootstrap capacitor C, a switch formed by a PMOS transistor 16 and an NMOS transistor 18, an inverter INV, and delay circuits D1 and D2. The gate of the pull-down transistor is coupled to receive the input clock signal IN. The gates of the switch transistors 16 and 18 are coupled to receive a delayed clock signal, and the capacitor is coupled to receive a further delayed and inverted clock signal. When the delayed clock signal reaches a first level, transistor 18 connects the gates of transistors 12 and 14 together, thereby pulling the output terminal OUT to approximately the supply voltage V.sub.DD. When the delayed clock signal reaches a second level, transistor 16 connects the gate of transistor 12 to the output terminal OUT, thereby allowing the bootstrap capacitor to boost the output terminal OUT beyond the supply voltage V.sub.DD.
The circuit 10 disclosed by Baba boosts the output terminal OUT to approximately V.sub.DD -V.sub.tP, where V.sub.tp, the threshold voltage of the pull-up transistor 12, is typically between approximately -0.7 and -1.0 volts. Since the pull-up transistor 12 is prone to latch-up or leakage due to forward biasing of the source and well of the transistor 12 at higher voltages, the maximum boosted voltage of the output terminal OUT is limited to approximately V.sub.DD -V.sub.tp.
FIG. 2 shows an output stage of a circuit for generating a boosted voltage of the type disclosed in U.S. Pat. No. 5,589,793, issued Dec. 31, 1996 to Kassapian. Circuit stage 20 includes a NOR gate G6 coupled to receive clock signals OSC and S2 and a delayed clock signal S1r. When the clock signal OSC transitions from high to low, signals S'1 and S2 transition from high to low, while signals S1 and S1r remain low. The output of logic gate transitions high, thereby turning on transistor Q1 which, in turn, charges capacitor C5 to a maximum voltage of V.sub.cc -V.sub.th, where V.sub.th is the threshold voltage of transistor Q1. Signal S1 then transitions from low to high, followed by the transitioning of signal S1r from low to high. As a result, transistor Q1 turns off and thereby isolates the output Philb from the supply voltage V.sub.cc. The output Phi1b is boosted by the charge on capacitor C5 to a maximum voltage of 2V.sub.cc -V.sub.th. Since at low voltages the maximum output voltage of the circuit stage 20, i.e., 2V.sub.cc -V.sub.th, is dominated by the threshold voltage V.sub.th, the Kassapian circuit is not well suited for low voltage applications. For instance, where V.sub.cc is equal to 1.5 volts, the maximum boosted voltage of the Kassapian circuit is only between approximately 2.0-2.3 volts.